1. Field of the Invention
The present invention relates to a memory cell and a semiconductor memory device having thereof memory cell, and particularly to a single memory cell configured by a transfer transistor, a load transistor, and a drive transistor.
2. Description of the Related Art
An SRAM (Static Random Access Memory) is one of semiconductor memory devices. Here, an example of a circuit of an SRAM is shown in FIG. 5. In an SRAM 100 shown in FIG. 5, a plurality of memory cells F1 to Fn are connected to a bit line pair configured by bit lines DT and DB. The memory cells F1 to Fn each include drive transistors 110, 111, drive transistors 120, 121, and transfer transistors 130, 131. Data are stored in storage nodes of connection points at each of which the drive transistor and the drive transistor are connected to each other, and read out by transfer of the data to the bit lines DT and DB via the transfer transistors.
Here, a timing chart of operations for reading data stored in a memory cell F1 is shown in FIG. 6. In an example shown in FIG. 6, storage nodes D01, D0n−1, D0n at the side of the bit line DT each are held at low level (for example, hold a ground voltage) while storage nodes E01, E0n−1, E0n at the side of the bit line DB each are held at a high level (for example, hold a power supply voltage), in the memory cells F1, Fn−1, Fn, respectively.
In the timing chart shown in FIG. 6, the level of a word line WL1 for selecting the memory cell F1 becomes high in a period from timing T11 to timing T12. Meanwhile, even in the period from timing T11 to timing T12, word lines WLn−1 and WLn selecting memory cells Fn−1 and Fn are held at low level. Therefore, in the period from T11 to T12, data is read from the storage nodes D01 and E01 of the memory cell F1 to the bit lines DT and DB. As a result of reading the data, the bit line DT changes to low level, but the bit line DB is held at high level.
However, in the SRAM 100, the storage nodes E0n−1 and E0n at the side of the bit line DB of the memory cells Fn−1 and Fn are held at low level, whereas the bit line DB changes to high level after the reading of data. Thus, a potential difference occurs between the source and drain of the respective transfer transistors 131 of the memory cells Fn−1 and Fn. Here, since the word lines WLn−1 and WLn are at low level, the transfer transistor 131s are in a nonconductive state, but a potential difference between the bit line DB and the storage node of each of the memory cells Fn−1 and Fn lets leak currents Ileak flow between the source and the drain of the transfer transistor 131 of each of the memory cells Fn−1 and Fn. Further, since there is substantially no potential difference between the bit line DB and the storage node E01 on the side of the bit line DB, the transfer transistor 131 is conductive, but is in a state equivalent to a nonconductive state. Thus, the bit line DB has a high impedance. Therefore, in the SRAM 100, the potential of the bit line DB which has to be held at high level is reduced. In the timing chart shown in FIG. 6 as well, the potential of the bit line DB is reduced in the period of the timing T11 to T12.
In recent semiconductor memory devices, an operating supply voltage is set low so as to reduce power consumption. Therefore, a potential difference between high level and low level in the bit lines DT and DB is small. Such a semiconductor memory device has a problem that, when a potential reduces in a bit line, a potential difference from another bit line cannot be detected correctly in a sense amplifier to which the bit lines are connected, so that a data read failure occurs.
Therefore, Japanese Patent Application Publication No. 2004-288306 (JP-A2004-288306) discloses a technique to prevent a potential reduction in a bit line from causing a data read failure. In JP-A2004-288306, the semiconductor memory device includes a leak detection line, a leak generation circuit, and a signal correction circuit in addition to memory cells and bit lines. The leak detection line is disposed in parallel to the bit lines. The leak generation circuit supplies a leak current to the leak detection line. The signal correction circuit detects a potential state of the leak detection line, and corrects a signal transferred via the bit line. That is, in JP-A2004-288306, the potential level of a signal transferred via the bit line is corrected based on the potential of the leak detection line having a potential reduction by a leak current, and on the potential of the bit line. In JP-A2004-288306, a data read failure is thus avoided even when the potential is reduced by a leak current in a bit line.
The following analyses are given by the present invention. In JP-A2004-288306, since the leak detection line, the leak generation circuit, and the signal correction circuit are added to the memory cells and bit lines, the circuit size is inevitably increased. Further, the leak generation circuit and memory cell are formed by use of different transistors, respectively. Therefore, it is likely that variation in transistors in manufacturing processes causes variation between a leak current amount generated in the leak generation circuit, and a leak current amount generated in the memory cell. That is, in JP-A2004-288306, the leak current amount of the memory cell may not necessarily correspond to the leak current amount of the leak generation circuit in some cases, which causes a problem of deteriorating a data read accuracy.